As known, EEPROM memories, while being a non-volatile type of memory, allow electrical modification of the information contained therein in either a write or an erase step. It is also known that each EEPROM cell comprises a floating gate transistor and a selection transistor. Once the selection transistor is enabled, it is possible to alter the state of the associated floating gate transistor, by exploiting a passage of electrons for tunnel effect through a thin layer of silicon oxide, the so-called tunnel oxide. Such a thin layer is provided below a portion of the floating gate region of the floating gate transistor, in which the charge is stored.
During the write and erase steps of the cells, positive voltages are usually applied to the diffusion below the tunnel region or to the control gate. Such voltages are between 8 and 18 Volts in order to generate a sufficiently high electrical field at the opposite ends of the thin oxide to activate the tunnel effect efficiently.
According to the prior art as shown in FIGS. 1-5, the matrix includes a structure 1′ comprising a plurality of rows 3′ and a plurality of columns 4′. Rows 3′ comprise Word Lines WL′1, WL′m. Columns 4′ instead comprise Bit Lines BL′ of the matrix and the Control Gate Lines CG′. Preferably, the Bit Lines BL′ are grouped in bytes, i.e. in groups of eight bits, BL′0. BL′7. In particular, each byte has an associated line CG′.
At the crossing of a word line WL′ and of a bit line BL′, a selection transistor 5′ is provided. Further on, a bit line BL′ connects together all the drain terminals of the selection transistors 5′ common to a given column 4′ of the matrix. Every selection transistor 5′ is associated and connected in series to a MOS floating gate transistor 2a′.
In more detail as shown in FIG. 3, the EEPROM memory cell 2′ comprises a MOS transistor 2a′ with a floating gate region 6′ wherein the charge is stored that allows the two different states of the cell to be distinguish: i.e. “written” or “erased”. A control gate region 7′, is capacitively coupled to the floating gate region 6′ through an intermediate, interpoly dielectric layer. Through such dielectric layer, voltage is transferred to the floating gate region 6′ from the control gate region 7′, during the write and/or erase steps of the cell 2′. The control terminal of the control gate region 7′ is common to all the cells 2′ forming a same byte in the structure 1′. The erasing of a byte is accomplished by addressing the word line WL′i corresponding to the desired i-th line and the control gate line CG′j corresponding to the selected byte.
The prior art process for making these memory cells on a P-type silicon substrate, with the control gate region self-aligned with the floating gate region, includes: the formation of active areas; the implantation of doped regions of N+ type; the formation of oxides of different thickness; the deposition and the following selective removal of a first layer of polysilicon for defining the floating gate regions in the direction of the Word Lines; the formation of an interpoly dielectric; the deposition and the following selective removal of a second layer of polysilicon for defining the control gate lines and the floating gate regions self-aligned to the control gate regions; and the implantation of the source and drain regions.
In order to achieve good operation of the matrix the control gate line CGj of each byte is required to be electrically separated from the control gate line of the other bytes. During the formation of the floating gate regions, the first layer of polysilicon between the floating gate regions belonging to adjacent cells of the same byte is removed; this step defines the floating gate regions in the direction of the line.
In order to minimize the area of each cell, it is desirable that the control gate lines of adjacent bytes be very close to each other. Therefore, during the above-described process step, the first layer of polysilicon is removed also by the source line portion common to two adjacent bytes. As previously described, after the above step is carried out, an intermediate oxide layer and then the second layer of polysilicon are formed, in order to make the control gate region. In order to make the final gate region of the floating gate transistor, a selective removal of the stack including the second layer of polysilicon, of the dielectric interpoly layer and of the first layer of polysilicon, is respectively carried out. This last removal is required in the process for making the final gate region and defines the length thereof.
In the portion of the source region common to two bytes, wherein the first layer of polysilicon has been removed during the first step of definition of the floating gates, the second step of removal of the first layer of polysilicon for defining the final gate region is not selective enough for discriminating the first layer of polysilicon or the surface of the substrate of silicon in single-crystal form. Therefore, the surface of the source region has notches 30 as shown in FIG. 5.
This surface arrangement of the common source region has various drawbacks. First of all, these notches may become receptacles for contaminating material, which would be hard to remove because of the small dimensions of the notches 30 themselves. Further, because of the differences in height present on the surface of the source region, the subsequent implantation of dopant provides non-uniform implanted region. This increases the resistance of the common source region. This drawback is particularly significant for the EEPROM parallel access memory matrices, because all the cells of the same byte will be read at the same time and thus the current in the common source region will reach relatively high values. This may lead to a read error on the single memory cell because of the resistance introduced by the presence of these notches.